1. Field of the Invention
The present invention relates to a data processor having an address translation circuit.
2. Description of the Related Art
The data processor which is the object of the present invention is an LSI chip including an arithmetic circuit such as a CPU and a digital signal processor or the like and a storage circuit, or is a board formed by a plurality of LSI chips. In the present specification, these circuits (CPU, DSP, or circuits which performs image information processing such as an MPRG decoder or a graphics processing circuit, or the like) which themselves issue an access request to other circuits are defined as master circuits, and conversely, these circuits (a memory or the like) which receive an access request from other circuits and perform processing are defined as slave circuits.
In recent data processors, the need for mounting an address translation circuit in addition to a master circuit and a slave circuit has been increased. The main reasons for this include the following two points.
Firstly, the first reason is caused due to the fact that the data processor has become to include a plurality of master circuits. Accompanied by higher function of application assisted by the improvement in the degree of integration of LSI, the function integrated on the LSI is increased, that is, the number of master circuits is increased. Also, since the master circuit has a slave circuit, if any countermeasure is not taken, the number of slave circuits will be increased as the master circuits become plural in number. However, in the data processor having a plurality of master circuits, since it is possible to reduce the overall cost of the data processor, if the master circuits can share the data mutually and if overlapped slave circuits can be reduced, the plurality of master circuits are made to share the slave circuit.
However, for example, the master circuits of CPUs, graphics processing circuits or the like have respectively inherent address maps. Here, the address map refers to the allocation of address indicating by which address each data is to be accessed, and respective master circuits have inherent address maps, and normally these address maps are different for each master circuit. Accordingly, in order to realize a data processor having a plurality of master circuits, it becomes necessary to change software. But, since a large amount of man-power and costs are required to change the software, it is beneficial to suppress the change to a minimum level as far as possible in view of the man-power of the programmer and the cost, even-though some extent of change of the software is unavoidable.
Therefore, in order to enable to use the already developed software with lesser program change, it is effective to use an address translation circuit. By connecting the address translation circuit between the master circuit and the slave circuit, the address contained in the request from the master circuit to the slave circuit is translated. For example, in a data processor including a CPU and a graphics processing circuit as the master circuit, address translation circuits will be respectively added to the output parts of the CPU and the graphics processing circuit.
Secondly, the second reason is caused by the need that the processing which requires a wider address space than that of the master circuit of the already existing CPU or the like is desired to be performed by the data processor using the existing master circuit. Specifically speaking, it corresponds to such a case in which the newest program of a large scale is desired to be executed by a CPU of one generation before.
As described above, the address translation circuit is a circuit which is connected between circuits having different address maps, and produces a translated address from the input original address.
Here, if the increase of the circuit scale of the address translation circuit is not disagreeable, the above-mentioned need will be met by an address translation method in which the address translation circuit is provided with a storage means for storing upper bits of the address after translation. That is, this is an address translation method in which a value stored in the above-mentioned storage means at the time of access of the master circuit is connected to lower bits of the address before translation thereby to form a translated address.
According to the above-mentioned address translation method, it is possible to dispose a certain region on the original address space on an arbitrary position on a translated address space, and also by updating the translated address information, it becomes possible to access from a narrow address space to a wider address space.
However, in the above-mentioned address translation method, at the time of access of the master circuit to a different part of the address space, since it is necessary to access after setting the address information storage, many changes are caused in the software which was produced for the existing circuit. Also, there is a drawback in which the processing speed is decreased due to updating of the translated address information storage.
Accordingly, the problem of the present invention is to reduce the changes in the software which has already been developed, in the data processor comprising a plurality of master circuits including a circuit having the software which has already been developed, and an address translation circuit in addition to one or a plurality of slave circuits shared by the plurality of master circuits, the address translation circuit being mounted between the plurality of master circuits and the slave circuits. Also, the problem is to suppress the increase of the circuit scale of the address translation circuit.
The above-mentioned problem or object, and novel features of the present invention will become apparent from the description in the present specification and the accompanied drawings.
In the invention disclosed in the present application, the outline of the typical aspect will be explained briefly.
That is, a data processor comprises a plurality of master circuits for issuing an access request to other circuits, one or more slave circuits upon receiving the access request from the master circuits for performing a processing, and an address translation circuit disposed between the master circuits and the slave circuits, for translating an original address output from the master circuits, and for outputting a translated address to the slave circuits, wherein the number of the address translation circuit is one or more, and is equal to or less than the number of the master circuits.
In the typical aspect of the invention mentioned above, in the case of the data processor where the slave circuits are shared by the plurality of master circuits, even when an address map is different for each master circuit, by providing the address translation circuit between the master circuits and the slave circuits, the address contained in the request from the master circuits to the slave circuits can be translated by the address translation circuit. Therefore, it is possible to use the software which has been already developed with less program change. This is very advantageous both in the man-power of the programmer and in the development cost of the software.
In the invention disclosed in the present application, the outline of another typical aspect will be explained briefly below.
A data processor typical in the present application, further comprises a translated address storage part; and the address translation circuit includes a plurality of address translation sub-circuits for independently performing address translation with respect to the original address, a circuit for selecting and outputting a translated address from a translation result of the plurality of address translation sub-circuits contained in the address translation circuit in accordance with address translation system selection information; and at least one of the address translation circuits receives as inputs address translation system selection information in addition to the original address from the master circuits, and the translated address information from the translated address storage part, and outputs the translated address to the slave circuits; and at least one of the address translation sub-circuits contained in the address translation circuit realizes an address translation system which produces the translated address by a method in which a part of the original address is replaced with translated address information stored beforehand in the translated address storage part; and at least one of the address translation sub-circuits contained in the address translation circuit realizes an address translation system which produces the translated address by a method including a permute manipulation of a part of the original address.
In the above-mentioned data processor, by constituting the data processor incorporating the address translation circuit which includes both of the circuits; one circuit realizing the address translation system by replacing a part of the original address with a value stored beforehand, and the other circuit realizing the address translation system by a method including the permute manipulation of a part of the original address, it enables the master circuit to perform the processing which requires a wider address apace than its own address apace. That is, such a processing can be performed by the data processor which uses the existing master circuit. By using the address translation circuit having two kinds of address translation systems, since there is no need to perform the address translation in which the storage means for storing the upper bits of the address after translation is included in the address translation circuit, the decrease of the processing speed is not caused, and it is possible to suppress the increase of the circuit scale of the address translation circuit.
Other objects, features and advantages of the invention will become apparent from the following description of the embodiments of the invention taken in conjunction with the accompanying drawings.